This invention relates to methods of manufacture of word line structures in a memory array in which information is stored and the structures formed thereby, and more particularly to DRAM (Dynamic Random Access Memory) arrays.
A memory array can be a part of a stand alone memory chip or can be a part of on-chip memory such as a memory cache of a microprocessor or digital circuit processor. “Random logic circuitry”, which comprises circuits that process information, may include “memory support circuitry” which provides read/write capability to and from a memory array. Random logic circuitry is not limited to “memory support circuitry” and could include arithmetic units, buses, latches, phase locked loops, etc. In a memory array there are word lines and bit lines which comprise the interconnect structures therein. A memory array consists of a plurality of individual memory cells with each cell having at least one “pass” or “access” transistor. Each “pass” transistor is gated by one of the word lines.
For the purpose of this invention, “word lines” are local interconnect structures created at the transistor gate level. Consequently, they are included, at least partially, as integral parts of a gate conductor structure or stack.
A gate conductor stack in a random logic circuitry serves as both the transistor gate and as a local interconnect. For instance, the gate conductor in a random logic circuit delivers an electrical signal from a gate contact to a remote portion of the adjacent logic transistor.
Because memory arrays are designed to be as dense as possible (thereby maximizing the amount of information stored per given chip area), the word lines are very narrow, long conductors which provide electrical connections between many memory cells. In a typical state-of-the-art memory array, a word line has a width of about 100 nm and connects hundreds of individual memory cells stretching longer than 10 μm in length. The word line width will continue to shrink in accordance with the general trends of miniaturization. At the same time, the length of word lines has been maintained as long as possible to allow simultaneous access to as many of the individual cells of the memory array, as possible. Subsequently, scaling down of word line lengths is not expected to be as fast as that of scaling down of the widths thereof. Therefore, the electrical resistance of word lines is becoming increasingly higher. One simple method of reducing the electrical resistance of word lines is to make them thicker. However, in the case of making them thicker, the capacitance per unit length becomes prohibitively high. Alternatively, a high aspect ratio (i.e. the ratio of line thickness to the line width) makes line etching processes less controllable, leading to an undesirable variation of line widths and/or sidewall profiles. A preferred method of reducing electrical resistance of word lines is to introduce new materials with higher electrical conductivities. Such new materials should be compatible with high-temperature processing (junction activation at 1000° C., for example) typically encountered at the gate level. Furthermore, such new materials should be compatible with transistor gate dielectric so that they do not introduce undesirable shifts in transistor performance.
Random logic transistors are typically designed to be superior switches meaning that a given “off current” their “on current” should be maximized. A high “on current” allows for a quick switching (charging or discharging) a load capacitance with a minimal dissipated power at a fixed “off current”. Further, a random logic circuit including local interconnects is designed for a minimum value of loading capacitance and for fast switching. Accordingly, the length of local interconnects is typically kept as short as possible in order to avoid introducing any extra delay time for transmission of signals of the kind associated with long local interconnects. Control of transistor gate length (related to the width of gate stack line) is directly related to the switching performance of a logic transistor. Factors affecting control of transistor gate length include planarity of the gate conductor layer, the aspect ratio of various dissimilar material layers present in the gate electrode stack, and the availability of selective Reactive Ion Etching (RIE) processes for dissimilar materials present in the gate electrode stack. Enhanced planarity is preferred. A low aspect ratio is also preferred. In addition, a higher etch selectivity is preferred.
Typically, a gate electrode structure that comprises a local interconnect runs over underlying isolation structures. For instance, a word line which connects multiple memory cells runs over isolation structures used to isolate various electrical elements (transistors, for instance) in memory cells and to isolate different memory cells.
Accordingly, the gate electrode stack material should be compatible with both the geometry and the material of which such isolation structures are composed to avoid inadvertent electrical short circuits (shorts) or open circuits (opens). Such electrical opens typically form when a portion of the gate local interconnect is missing due to either loss of adhesion, severe overetching, or inability to maintain continuity during the deposition process (poor step coverage during deposition, for instance). Electrical shorts typically form when a gate material has not been completely cleared during local interconnect etching, or, alternatively, when an underlying isolation structure has been severely overetched allowing for an inadvertent electrical connection to surrounding conductive structures.
Because of different design objectives, the gate conductor structure can be beneficially different in memory array(s) and random logic circuits. In that case, the gate conductor structures should meet compatibility requirements not to degrade performance of either memory array or random logic circuitry. Desirably, prior to gate level patterning, the gate conductor layer should be as planar as possible. It is also desirable that a RIE process should be able to etch dissimilar array/logic gate structures simultaneously, without introducing undesirable effects such as gate dielectric punch through, isolation punch through, electrical shorts due to incomplete etch, and electrical opens due to an overetch. Desirably, both conductor structures should be compatible with respective gate dielectrics such that both “pass” transistor and logic transistor do not have undesirable shifts in performance. It is also desirable that both conductor structures should be compatible with underlying isolation structures such that there is no loss of adhesion between the gate conductors and respective isolation structures.
Polysilicon-metal silicide gate electrode structures are widely used to reduce electrical conductivity of gate conductors. Polysilicon is a high temperature stable material compatible with a typical gate dielectric and isolation dielectric materials. Metal silicide possesses a metallic type of conductivity providing low resistance for the gate electrode stack. In one example, the metal silicide is a tungsten silicide (WSi) deposited over a polysilicon layer. Such a conductive stack comprised of polysilicon and deposited silicide is typically referred to as “polycide”. The polysilicon layer thickness is selected to be as small as possible thereby preventing increasing gate electrode stack aspect ratio and/or capacitance but at the same time it is selected to be thick enough for etching WSi layer without compromising any underlying dielectric structures. In addition, the polysilicon layer should be thick enough to substantially block diffusion of fluorine (F) gas or elemental fluorine if the tungsten silicide deposition process employs tungsten hexafluoride (WF6) gas as a tungsten precursor.
Polysilicon-metal gate electrode structures provide a further reduction in electrical resistance because electrical conductivity of elemental metal films is generally larger than that of metal silicides. Refractory elemental metals such as tungsten (W), molybdenum (Mo), and tantalum (Ta) are typically employed in polysilicon-metal gate electrode structures. A thin conductive diffusion barrier is typically disposed between the polysilicon and the elemental metal to prevent silicidation of the elemental metal during high-temperature processing. The diffusion barrier is typically comprised of conductive metal nitrides such as tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN) and/or respective silicon-containing ternary compounds such as WSiN, TiSiN, and TaSiN. In addition, an ultra thin quantum conductive barrier made of otherwise insulating material such as silicon nitride can also be included into the conductive diffusion barrier. One particularly useful example is a polysilicon-barrier-W gate stack where the barrier is composed of tungsten nitride (WN). In this example, RIE of tungsten has a poor selectivity to an underlying polysilicon layer meaning that the polysilicon layer etches with about the same speed as the tungsten (W) layer. Further, RIE of tungsten (W) requires a large overetch typically up to 100% to completely clear tungsten (W) from around the steps formed by isolation structures. Due to poor etch selectivity between polysilicon and tungsten (W) and a requirement of tungsten layer overetch, the polysilicon thickness is selected to be larger than that of the tungsten (W) layer to avoid any gate dielectric punch through.
FIG. 1. shows a sectional view of a prior art DRAM device 8 of the kind described in a paper by Rama Divakaruni et al. entitled “Gate prespacers for high density DRAMs International Symposium on VLSI Technology Systems and Applications Taipei, Taiwan 8–10 (June 1999). The device 8 includes an array region on the left and a support region on the right, with the two regions being spaced apart as indicated by the break away lines in the center. A silicon substrate 11A/11B includes active areas 11A in the array region and doped silicon 11B in the support region.
In the array region, a doped polysilicon stud 12 is shown formed on the top of a deep trench above a storage capacitor, not shown. The upper portion of the deep trench is lined on the sidewalls thereof by dielectric regions 14 with a vertical gate oxide layer (vGOX) layer 40 which lines the sidewalls of the trench therebelow. In its lower portion, the polysilicon stud 12 is directly adjacent to the vertical gate oxide layer (vGOX) 40 trench as is well understood by those skilled in the art, thereby forming the gate electrode of a vertical transistor. On either side of the active areas 11A near the top surface of the substrate 11A are the dielectric regions 14 with an Array Top Oxide (ATO) region 15 on the top surface of the active areas AA, between the dielectric regions 14.
Three word line stacks 26A, 26B and 26C comprising polycide conductors 21P capped with silicon nitride caps 22, i.e. Cap Nitride (CN), are formed on top of the left hand and right hand ATO regions 15 and in the middle above the stud 12. The polycide conductors 21P are isolated from the active areas AA by the ATO 15 on the right and the left, but the polycide conductor 21P of the central word line stack 26B is in contact with the stud 12. Accordingly the stud 12 and polycide conductor 21P on top of it comprise, the integrated gate stack 26B of a vertical “pass” transistor. The top of the stud has a recess 30 formed between the base of the polycide conductor 21P of the central word line stack 26B and the adjacent dielectric region 14.
In the support region, on the right of FIG. 1, the top surface of the substrate 11B is covered with a Gate OXide (GOX) layer 17. Above the GOX layer 17 a gate electrode stack 27 is shown comprising a gate electrode comprising a doped gate polysilicon layer 18 formed on the surface of the GOX layer 17 and a polycide conductor 21P thereabove which in turn is capped by a cap nitride (CN) layer 22.
FIG. 2 shows a device 9 which is a modification of the device 8 of FIG. 1 in accordance with the paper by Akatsu et al. entitled “A highly manufacturable 110 nm DRAM technology with 8F2 vertical transistor cell for 1 Gb and beyond”, Symposium on VLSI Technology, P52, (2002).
In FIG. 2 all of the elements of FIG. 1 are shown with the modification that there are silicon nitride spacers 25 formed on the sidewalls of the stacks 26A–26C in the array region and on the sidewalls of the gate electrode stack 27 in the support region. In addition, the conductors 21A comprise a WN/W metallic bilayer, not the polycide conductors 21P of FIG. 1. Accordingly, the resistance of a gate stack (or word line) shown in FIG. 2 is about from 2 to 4 times lower than that of FIG. 1 while maintaining similar stack (or word line) capacitance.
Akatsu et al. teach a dense memory array with vertical pass transistors, thick top oxide isolation structures, barrier-W word lines, and polysilicon-barrier-W gates. Akatsu et al. also teach an integration of such dense memory array with random logic circuitry comprised of transistors with polysilicon-barrier-W gates. In the memory array, vertical pass transistors are formed on the walls of respective trenches made in the silicon substrate.
In FIG. 2, a conductive polysilicon plug 12 filled into the top portion of a trench forms a gate of a vertical pass transistor. The polysilicon plugs 12 of individual trenches are connected by a word line 26B which runs over the trenches, top oxide isolation structures, and isolation trenches. The word line 26B is composed of a WN/W metallic bilayer 21A. In the logic circuitry, the gates of transistors are composed of polysilicon-barrier-metal structure. In order to improve planarity of the gate conductor layer, the thickness of the top oxide in the array is chosen to be close to that of the polysilicon layer in the logic circuitry area. Akatsu et al. teach that a non-planar structure may exist in the transition region between memory array and logic circuitry; and that, in the logic circuitry; the polysilicon layer was made substantially thicker than that the metal layer to avoid gate dielectric punch through.